用序列模型解决芯片设计中时序预测的可扩展性难题
RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm
- 将逻辑锥结构按广度优先遍历线性化，适配序列模型处理
- 在多个基准上实现比现有方法更优的时序预测精度
- 适合芯片前端设计优化人员快速评估电路性能
准确的寄存器传输级（RTL）时序预测是电子设计自动化中的长期挑战。现有基于图的方法存在感受野有限、计算复杂度高及缺乏信号方向性的缺陷。本文提出RTL-Sequencer，一种新型序列范式，通过广度优先遍历线性化逻辑锥结构，并应用现代线性序列模型实现可扩展的RTL时序预测。此外，序列模型通过四种协同技术进行定制：序列打乱、双向建模、可微建模以及混合图-序列架构。大量实验表明，RTL-Sequencer在多个基准上显著优于当前最优基线，推动了早期阶段时序优化的发展。
原文摘要 · Abstract (English)
Accurate timing prediction at the register-transfer level (RTL) is a longstanding challenge in design automation. Existing graph-based methods struggle with limited receptive fields, high complexity, and a lack of signal directionality. We present RTL-Sequencer, a novel sequence-based paradigm that enables scalable RTL timing prediction via linearizing logic cones by breadth-first traversal and applying modern linear sequence models. Furthermore, sequence models are customized by four synergistic techniques, including sequence shuffling, bidirectional modeling, differentiable modeling, and a hybrid graph-sequence architecture. Extensive experiments demonstrate significant improvements of RTL-Sequencer over state-of-the-art baselines, advancing early-stage timing optimization.
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