在智能处理器上首次实现3D高斯渲染，探索无显存架构的可行性。
Rendering 3D Gaussians on a Graph Processor
- 将3D高斯映射分块到IPU的1472个核心，通过曼哈顿距离路由至目标区域。
- 在仅用片上SRAM的条件下，实现高效渲染，但受带宽和存储容量限制。
- 适合关注低功耗、无外显存渲染系统的研究者与硬件设计者。
我们首次在智能处理单元（IPU）上实现了3D高斯渲染，该IPU包含1,472个独立计算单元，仅依赖片上SRAM，模拟高效传感器-处理器架构的特性。输入场景为真实序列生成的3D高斯地图。每个计算单元负责帧缓冲区的一个屏幕空间区域；高斯基元通过南北东西（NEWS）网格按曼哈顿距离跳转，再以扩展树模式分发给重叠邻居。计算遵循IPU的批量同步并行（BSP）模型，跨核心通信在编译时定义。实验表明，该硬件可利用空间与时间局部性，实现核心间本地数据传输。我们评估了此纯SRAM实现中的瓶颈：跨核心带宽、每单元SRAM容量以及非均匀高斯密度导致的工作负载不平衡。分析揭示这些约束对性能与渲染质量的影响。研究引发对传统GPU与3D表示的反思，暗示直接的SM间通信可能减少GPU内核对主存的访问。讨论对未来传感器级与无主存架构的意义。项目页面：https://nmjfry.github.io/ipu-3dgs/
原文摘要 · Abstract (English)
We present the first implementation of a 3D Gaussian renderer on an Intelligence Processing Unit (IPU), comprising 1,472 independent tiles with only on-chip SRAM; constraints that approximate properties of efficient sensor-processor architectures. Our input scenes are 3D Gaussian maps from real-world sequences. Each tile 'owns' a screen-space region of the framebuffer; Gaussian primitives are routed to destination tiles via Manhattan-distance hops on a north-east-west-south (NEWS) grid, then distributed to overlapping neighbours in an expanding tree pattern. Computation follows the IPU's Bulk Synchronous Parallel (BSP) model, with inter-tile communication defined at compile time. We show this hardware allows us to exploit spatial and temporal locality by enabling local data transfer between cores. We evaluate the bottlenecks in this SRAM-only implementation: inter-tile bandwidth, per-tile SRAM capacity, and workload imbalance from non-uniform Gaussian density. We analyse how these constraints affect performance and render quality. This exploration raises broader questions for conventional GPUs and 3D representations, suggesting that direct inter-SM (streaming multiprocessor) communication might offer ways to reduce DRAM access in GPU kernels. We discuss these implications for the future of on-sensor and DRAM-free architectures. Project page: https://nmjfry.github.io/ipu-3dgs/
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