优化手机NPU推理时的电流峰值，提升低电量下运行稳定性。
Mitigating Compiler Fusion-Induced Power Bursts in Mobile NPU Inference as the Battery Depletes
- 通过预编译图重写，在热点处插入屏障防止算子过度融合。
- 峰值电流从3.12A降至1.94A，延迟增加3.76%。
- 使低电压下延迟更稳定，DVFS触发点提升约173mV，适合移动端推理优化者。
移动设备日益依赖NPU进行实时图像与感知任务。在低电压条件下，单次推理可能引发电源网络瞬时电压下降，导致电源管理芯片启动动态电压频率调节（DVFS），增加延迟。我们对商用智能手机进行了测量研究，发现移动端NPU编译器中激进的算子融合会生成集中执行的巨型算子层（superlayers），造成显著的电流峰值。这些峰值使DVFS触发电压升高，缩小了低电压工作余量。我们提出一种实用的黑盒缓解方法：基于测量的预编译图重写，在峰值-平均功率比热点处插入屏障，阻止有害的算子层合并。在搭载Snapdragon 8 Gen 3的设备上，以MobileNetV4在ImageNet-1k 768×768分辨率下测试，该方法将峰值电流从3.12A降至1.94A，延迟仅增加3.76%，维持了更低电压下的稳定延迟，并使推断出的DVFS余量提升约173mV。
原文摘要 · Abstract (English)
Mobile devices increasingly rely on real-time NPU inference for camera and perception workloads. Under low-voltage conditions, however, a single inference can induce an instantaneous voltage droop in the power-delivery network, causing the power management integrated circuit to invoke dynamic voltage and frequency scaling (DVFS) and increase latency. We present a measurement study of this effect on a commercial smartphone. We show that aggressive operator fusion in a mobile NPU compiler can create monolithic superlayers whose concentrated execution produces large peak-current bursts. These bursts shift the DVFS-onset voltage upward and reduce the low-voltage operating margin. We further evaluate a practical black-box mitigation: a measurement-guided, pre-compilation graph rewrite that inserts barriers at selected peak-to-average power ratio hot spots to prevent harmful superlayer merging in the vendor NPU compiler. On Snapdragon 8 Gen 3 with MobileNetV4 at 768 x 768 resolution on ImageNet-1k, this method reduces peak current from 3.12 A to 1.94 A with 3.76% latency overhead, preserves stable latency deeper into the low-voltage regime, and shifts the inferred DVFS margin by approximately 173 mV.
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