用逻辑门网络实现低延迟脑电分类，适合边缘设备部署
Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices
- 将神经网络转为纯布尔电路，用位运算替代浮点计算
- 在4个数据集上，痴呆检测准确率达80.2%，比MLP高6.8%
- 模型越大越快，最大提速2.9倍，内存仅1/14
边缘设备上的实时脑电信号分类受限于传统神经网络的浮点运算。本文研究了可微逻辑门网络（Diff-Logic），这是一种硬件原生的替代方案，可将模型编译为可通过位运算执行的纯布尔电路。在四个脑电数据集上，涵盖二分类痴呆检测与三分类情绪识别任务，我们对匹配容量的多层感知机（MLP）和二值化神经网络（BNN）进行了跨四类复杂度（50k–500k参数）的对比实验。在痴呆筛查中，Diff-Logic取得80.2%宏F1，优于MLP基线6.8%。在情绪识别中，尽管MLP性能略优，但其部署于7W功耗的Nvidia Jetson Orin Nano单核CPU时，延迟高出2.3倍，模型体积大14倍。关键的是，Diff-Logic推理时间随模型规模增加基本不变，在最大复杂度下相比MLP最高提速2.9倍。结果表明，基于逻辑的神经架构是资源受限脑机接口的可行方案，可在满足延迟与内存约束的同时实现竞争性或更优性能。代码已开源：https://github.com/Shyamal-Dharia/eeg-difflogic
原文摘要 · Abstract (English)
Real-time EEG classification on edge devices is bottlenecked by the floating-point arithmetic of conventional neural networks. We investigated Differentiable Logic Gate Networks (Diff-Logic) as a hardware-native alternative that compiles models into pure Boolean circuits executable via bitwise CPU operations. Through rigorous iso-parameter experiments across four EEG datasets spanning two classification tasks, binary dementia detection and 3-class emotion recognition, we compared Diff-Logic against matched-capacity Multi-Layer Perceptron (MLP) and Binarized Neural Network (BNN) baselines at four complexity tiers (50k-500k parameters). On dementia screening, Diff-Logic achieved 80.2% Macro F1, outperforming the MLP baseline by 6.8%. On emotion recognition, the MLP retained a moderate performance advantage but incurred a 2.3$\times$ higher latency and 14$\times$ larger model size when deployed on a power-constrained (7W) Nvidia Jetson Orin Nano CPU (Single-core). Critically, Diff-Logic inference time remained nearly constant across a 10$\times$ increase in model scale, achieving a peak speedup of 2.9$\times$ over MLPs at the largest complexity tier. Our results establish logic-based neural architectures as a practical paradigm for resource-constrained brain-computer interfaces, achieving competitive or superior performance while natively satisfying the latency and memory constraints of portable edge deployment. Code is available on GitHub: https://github.com/Shyamal-Dharia/eeg-difflogic
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