为芯片组AI系统提出可靠晶粒筛选的数学框架，确保封装后寿命可靠性。
Formal Foundations for Known Good Reliable Die Screening in Chiplet-Based AI Systems-on-Chip
- 将晶粒筛选建模为不完备观测下的约束推断问题
- 模拟4000个晶粒验证安全保证在全阈值范围内成立
- 适合芯片可靠性验证与AI SoC设计团队参考
芯片组式人工智能系统芯片（SoC）的快速发展暴露了半导体测试方法的根本缺陷。现有已知良品晶粒（KGD）筛选可保证组装前功能正确性，但无法提供组装后可靠性的概率保障。本文将从KGD到已知良品可靠晶粒（KGRD）的过渡形式化为一个受限推断问题，建立在不完全组装前可观测性基础上。提出了四项相互关联的贡献：(i) 基于贝叶斯的概率风险模型，将组装前遥测数据映射为组装后故障概率，并给出可量化的可观测性偏差边界；(ii) 安全门控决策架构，提供可证明的组装后故障概率保证；(iii) 基于贝叶斯最优决策理论得出的不确定性感知处置边界；(iv) 受限闭环反馈机制，在不违反可靠性约束的前提下实现模型持续改进。对N=4,000个合成晶粒的蒙特卡洛仿真验证了所有四项理论性质，并确认安全保证在全部测试门限范围内保持一致。
原文摘要 · Abstract (English)
The rapid growth of chiplet-based artificial intelligence systems-on-chip (SoCs) has exposed a fundamental gap in semiconductor test methodology. Existing Known Good Die (KGD) screening guarantees pre-assembly functional correctness, yet it offers no probabilistic assurance of post-assembly reliability lifetime. To address this limitation, the present work formalizes the transition from KGD to Known Good Reliable Die (KGRD) screening as a constrained inference problem over incomplete pre-assembly observability. Building upon this formulation, four interlocking contributions are presented: (i) a Bayesian probabilistic risk model that maps pre-assembly telemetry to post-assembly failure likelihood with a quantified observability bias bound; (ii) a safety-gated decision architecture that provides a provable post-assembly failure probability guarantee; (iii) uncertainty-aware disposition boundaries derived from Bayes-optimal decision theory; and (iv) a constrained closed-loop feedback mechanism that delivers consistent model improvement without violating reliability constraints. A Monte Carlo simulation study on N = 4,000 synthetic dies verifies all four theoretical properties and confirms that the safety guarantee holds uniformly across the full range of tested gate threshold.
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