在资源受限的RISC-V单核上实现浮点16训练，内存减半且性能损失小。
Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core
- 利用RISC-V的浮点16扩展指令，设计软硬件协同框架。
- 相比32位浮点，内存占用降低约50%，模型性能损失极小。
- 适合嵌入式设备上的模型微调与迁移学习，支持层冻结。
通过利用标准RISC-V扩展Zfh（标量浮点16）和Zvfh（向量浮点16），本文提出一个开源框架，实现在资源受限的RISC-V单核上的完整本地训练。该方法相比使用float32可将内存占用减少约50%，且模型性能下降极少。同时，通过引入层冻结能力，支持迁移学习与微调场景。工作基于AIfES——一个面向嵌入式系统的开源、模块化通用深度神经网络训练与推理框架，可扩展自定义硬件函数。Zfh在RV64GC超标量乱序FPGA软核上仅带来+1.15% LUT6和+0.05% FF的面积开销（175MHz）。最后，讨论了在同一流水线中实现Zvfh的架构设计。
原文摘要 · Abstract (English)
By leveraging standard RISC-V extensions, namely Zfh (scalar float16) and Zvfh (vector float16), this work proposes an open-source framework to enable complete on-device training on resource-constrained RISC-V single-core. Our approach allows memory footprint reduction by about 50% as compared to using float32 and with minimal model performance degradation. We also facilitate transfer learning and fine-tuning scenarios by incorporating layer-freezing capabilities. Our work builds onto AIfES, an open-source, modular and generic DNN training and inference framework for embedded systems that can be extended with custom hardware-specific functions. The benefits of float16 is further emphasized by outlining the low area overhead of Zfh on a RV64GC super-scalar out-of-order FPGA softcore (+1.15% LUT6 and +0.05% FF at 175MHz). Finally, we discuss the architecture of a Zvfh implementation within the same RISC-V core.
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