用大模型自动修复芯片版图设计违规，准确率超92%。
DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models
- 构建闭环智能体框架，结合规则引擎与大模型选择几何修正方案。
- 在FreePDK45数据集上实现92.5%的完全修复率，总违规减少98%。
- 适合芯片设计自动化领域研究者，尤其关注AI辅助验证的团队。
版图设计规则违例（DRVs）的修复需反复进行几何修改与验证。本文提出DRC-Aid，一个闭环智能体框架，将修复过程建模为验证驱动的搜索。通过确定性规则引擎将物理验证工具报告的违规转化为有限的几何修改选项，再由现成的大语言模型（LLM）基于局部几何上下文从该菜单中选择操作，配合有预算的深度优先搜索与回溯。Calibre nmDRC/nmLVS等验证工具提供即时反馈，确保几何合规并防止电学拓扑退化，全局记忆库避免循环探索。在包含违规的FreePDK45版图上测试，DRC-Aid在约92.5%的情况下实现无错（DRC-clean）且与LVS等价的修复，总违规减少约98%；剩余案例生成部分修复的等价候选。在相同搜索与验证环境下，基于LLM的选择优于随机策略（54.4%）和确定性启发式策略（83.3%），尤其在六处以上违规时差距更大。
原文摘要 · Abstract (English)
Resolving Design Rule Violations (DRVs) in layouts entails an iterative loop of geometric edits and verification. We present DRC-Aid, a closed-loop agentic framework that automates local DRC repair by formulating it as verification-in-the-loop search. To constrain the combinatorial geometric repair space, a deterministic Rule Engine converts physical verification tool-reported violations into a bounded menu of geometric edits. An off-the-shelf Large Language Model (LLM) evaluates local geometric context to select edits from this menu, with budgeted depth-first search and backtracking. Immediate feedback from verification tools such as Calibre nmDRC/nmLVS enforces geometric compliance and guards against electrical-topology degradation, while a global Memory Bank prevents cyclic re-exploration. Evaluated on FreePDK45 layouts containing DRVs, DRC-Aid achieves DRC-clean, LVS-equivalent repairs in ~92.5% of cases with a ~98% total violation reduction, while residual cases yield partially repaired LVS-equivalent candidates. Under an identical search and verification infrastructure, LLM-based selection outperforms random (54.4%) and deterministic-heuristic (83.3%) policies, with the gap widening on cases with six or more violations.
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