用图嵌入技术加速大规模芯片木马检测，提升准确率与效率。
ADVERSARIAL: And-Inverter Graph-Assisted Hardware Trojan Detection At Scale
- 将电路网表转为有向边的符号化图结构，实现高效建模。
- 在真实芯片数据上实现木马节点与正常节点的几何分离。
- 适合需要高精度、可扩展性硬件安全检测的工程师使用。
现代片上系统（SoC）包含数亿至数百亿个门，现有硬件木马（HT）检测方法因规模过大而难以应用。本文提出的方法通过将扁平化的门级网表建模为布尔网络，以与非反相图（AIG）表示，其中所有内部节点为双输入与门，反相操作位于边中。每个有向连接在知识图嵌入（KGE）框架下表示为三元组，生成紧凑的固定大小节点表征，保留多跳结构上下文。由于AIG具有有限扇入和统一语义，训练与推理复杂度随边数线性增长，有效解决木马检测中的可扩展性瓶颈。跨深度数据路径的符号化学习使模型能区分罕见且功能不一致的连接——这些往往是潜在木马触发器与载荷的特征。在大规模SoC基准测试中，实验显示木马节点与良性节点间存在清晰几何分离，验证了方法的实际可扩展性。
原文摘要 · Abstract (English)
Modern System-on-Chip (SoCs) often contain hundreds of millions to tens of billions of gates, making existing Hardware Trojan (HT) detection methods impractical due to their immense scale. The proposed approach incorporates symbolically enabled learning by modeling flattened gate-level netlists as Boolean networks represented as And-Inverter Graphs (AIGs), where all internal nodes are 2-input AND gates and inversions reside on the edges. Each directed connection is expressed as a triple within a Knowledge Graph Embedding (KGE) framework, producing compact, constant-size per-node representations that retain multi-hop structural context. The AIG's bounded fan-in and uniform semantics ensure training and inference complexity scale linearly with edge count, addressing major scalability bottlenecks in HT detection. Symbolically enabled learning across deep datapaths enables the model to differentiate circuit structures from rare and functionally inconsistent connections that signify potential Trojan triggers and payloads. Experiments on large-scale SoC benchmarks demonstrate clear geometric separation between Trojan and benign nodes and practical scalability.
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