arXiv:2607.24819eess.SPcs.AI2026-07

提出动态瓶颈评估方法,实时识别晶圆制造中关键瓶颈。

Dynamic Multi-Criteria Bottleneck Severity Index (DMBSI) for Semiconductor Wafer Manufacturing: A Genetically Optimised Framework for Reentrant Production Systems

  • 基于多指标数据融合与遗传优化,构建动态瓶颈指数。
  • 相关性达0.80,较专家经验提升8.1%,显著优于传统方法。
  • 可追踪瓶颈随时间迁移,适合制造优化与产线调度决策者。

晶圆制造具有重入式流程、动态瓶颈和高度变化的工艺条件等独特特征。为实时识别半导体晶圆制造中的最严重瓶颈,本文提出一种新的数据驱动方法——动态多准则瓶颈严重度指数(DMBSI),通过分析周期时间对工艺参数变化的响应及返工对周期时间的影响,生成可解释的统一瓶颈严重度度量。在Seagate Technology一家200mm晶圆厂的22批生产数据上进行5折交叉验证,经遗传算法优化的DMBSI与实际周期时间贡献的相关系数达到r = 0.80,比专家启发式基准(r = 0.74)提升8.1%,显著优于约束理论(TOC;r = 0.60)和价值流图(VSM;r = -0.30)。此外,DMBSI的时间窗口设计揭示了瓶颈迁移规律:早期以介电沉积步骤为主导,后期转向过检与欠检问题。反事实分析显示,若顶级瓶颈步骤等待时间减少50%,平均周期时间将下降7.2%,前五个瓶颈步骤合计有约19%的优化潜力。

原文摘要 · Abstract (English)

Wafer fabrication exhibits unique characteristics, including reentrant process flows, variable bottlenecks, and highly variable process conditions. In order to identify the most severe bottleneck at each moment in time for semiconductor wafer fabrication, this research presents the Dynamic Multi-Criteria Bottleneck Severity Index (DMBSI), a new, data-driven methodology for analysing multiple diagnostic signals of cycle time to changes in process parameters, and the impact of reworks on cycle time in order to generate an interpretable, unified measure of bottleneck severity. The experimental validation of DMBSI was conducted using Manufacturing Execution System (MES) logs collected from 22 wafer production lots at a commercial 200 mm wafer fabrication line operated by Seagate Technology. Using 5-fold cross-validation, the GA-optimised DMBSI achieves a Pearson correlation of r = 0.80 with observed cycle-time contributions, representing an 8.1% improvement over the expert heuristic baseline (r = 0.74) and substantially outperforming the Theory of Constraints (TOC; r = 0.60) and Value Stream Mapping (VSM; r = -0.30). Furthermore, the unique time-windowed component of DMBSI enabled the identification of temporal bottleneck migration patterns, which shifted from the dominant constraints associated with dielectric deposition steps in the early production windows to those associated with over- and under-inspection in the later production windows. The integrated what-if counterfactual analysis demonstrated that a 50% reduction in waiting time at the top-ranked bottleneck step would reduce the mean cycle time by 7.2%, with the top five bottleneck steps offering a combined potential reduction of approximately 19%.

制造优化瓶颈分析遗传算法晶圆制造

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