用忆阻器实现高速分支预测，提升处理器性能。
Investigating reservoir computing for branch prediction in pipelined processors using emerging CMOS memristor devices
- 基于忆阻器构建新型储层计算框架，适配流水线处理器
- 在RISC-V指令集上实现98%以上预测准确率
- 适合追求能效比的未来芯片设计者参考
本项目旨在开发一种面向多级流水线中央处理器核心分支预测（BP）任务的新型储层计算（RC）实现框架，具备高速运行与CMOS数字逻辑集成能力。为此，提出了一种基于忆阻器的RC设计框架，并采用业界标准的System Verilog（SV）和Verilog-AMS（VAMS）进行仿真实现。该框架首先通过基础序列检测任务验证，随后在针对RISC-V RV64GC指令集架构的Dhrystone性能基准测试中评估其有效性。测试表明，该RC方法在分支预测中展现出巨大潜力，整体预测准确率超过98%。然而，与当前最优的TAGE预测器相比，其适应分支行为变化的速度慢15倍，表明需进一步优化框架以提升自适应能力。
原文摘要 · Abstract (English)
This project aimed to develop a novel reservoir compute (RC) implementation framework targeting high-speed operation and integration with CMOS digital logic. With the target workload of branch prediction (BP) for multistage pipelined central pro-cessing unit (CPU) cores. For this, a novel memristor based RC design framework was developed within the context of the workload requirements. This was then implemented in simulation using industry standard modelling languages of System Verilog (SV) and Verilog-AMS (VAMS).The developed RC design framework was subsequently verified using a basic sequence detection task before further benchmarking for its effectiveness at BP. The developed RC framework was tested using the Dhrystone performance benchmark, while targeting the RISC-V RV64GC instruction set architecture (ISA). Conducted testing demonstrates that RC shows great promise for ap-plication to BP and is capable of achieving impressive overall prediction accuracy. However, testing also shows that further refinement of the developed RC design framework is necessary to address shortfalls in the adaptability of the proposed RC system. As comparison against the state of the art TAGE predictor showed the proposed RC design framework to be 15x slower to adapt to changes in branching behaviour.
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