机器学习预测器在微架构设计中难以准确排序配置性能，尤其在局部反转场景下失效。
On the Limits of Machine-Learned Ranking for Modern Microarchitectural Policies
- 用机器学习预测硬件配置性能排序，但对细微差异敏感度不足。
- 22.4%的配置对比出现反直觉性能反转，且无法稳定预测。
- 模型在小差异场景表现差，仍需循环级仿真获取关键洞察。
机器学习预测器可比周期级模拟更快估算处理器性能。但在设计空间探索中，真正重要的是识别不同硬件配置在程序各阶段的性能排序。本文评估了四种机器学习预测器在两种设计范式下的表现：结构性参数（SP）——改变指令发射宽度、重排序缓冲区大小、缓存容量；行为策略（BP）——改变预取和替换算法。在SP范式中，整体排序效果良好，但存在22.4%的反直觉窗口（CIW），即预期较慢的配置反而更快，跨五组配置对的匹配率仅23.3%–39.9%，均低于50%的随机基线。在BP范式中，真实性能平局占37.8%的配置窗口，多数配置差异仅几周期，且无模型家族能稳定超越无需特征的多数基线。NeuroScalar与SimNet表现更差，Concorde与基线统计上无差异，最佳的OneDSE头仅提升2.1个百分点。准确性提升主要出现在大差异场景。进一步的信息论分析表明，当排序结果依赖于指令流中不可见的微架构状态时，任何基于轨迹的预测器都无法超过由可观测输入决定的贝叶斯最优精度。因此，高周期或整体排序精度可能仅反映对易处理大差异情况的掌握，而忽略了最具架构洞察力的局部反转，此时周期级模拟依然不可或缺。
原文摘要 · Abstract (English)
Machine-learning predictors estimate processor performance far faster than cycle-level simulation. For design-space exploration, however, the valuable test is not merely reproducing the usual hardware ordering, but identifying how different hardware configurations rank on individual program phases. We evaluate four ML-predictors in two design regimes: \emph{Structural Parameters} (SP), varying hardware resources such as issue width, ROB size, and cache capacity; and \emph{Behavioral Policies} (BP), varying prefetching and replacement algorithms. In the SP regime, aggregate ranking is strong, yet counter-intuitive windows(CIW)---where the configuration expected to be slower is faster---constitute $22.4\%$ of non-tied windows across five pairs with a clear architectural prior. CIW match across these pairs is only $23.3$--$39.9\%$; every point estimate is below the $50\%$ random strict-ordering reference. The BP regime presents a different failure: ground-truth ties cover $37.8\%$ of pair-windows, most strict pairs have margins of only a few cycles, and no model family reliably beats a feature-free majority baseline. NeuroScalar and SimNet fall below that baseline, Concorde is statistically tied with it, and the best selected OneDSE head improves by only $2.1$ percentage points. Accuracy rises mainly at large margins. We further show that this failure is not a matter of model capacity: an information-theoretic analysis reveals that when ranking outcomes depend on hidden microarchitectural state absent from the instruction stream, no trace-based predictor can exceed the Bayes accuracy determined by observable inputs alone. Thus high cycle or aggregate ranking accuracy can reflect mastery of easy, high-margin cases while missing the local reversals that carry the most architectural insight and for which cycle-level simulation remains indispensable.
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