让电路像生物一样自修复，动态重连逻辑应对硬件故障
Self-Organising Digital Circuits
- 用图注意力网络动态配置逻辑门，实现电路自组织
- 对永久性故障可快速重构，软错误恢复准确率超99.99%
- 能泛化到更大规模电路，适合高可靠性硬件设计
经典计算中的容错依赖静态策略如硬件冗余和纠错码。生物系统则通过动态重组维持功能。受此启发，我们提出自组织数字电路，将逻辑功能生成与维护建模为图上的元学习问题。架构采用拓扑掩码Transformer，配置电路中布尔门的查找表（LUT）。借鉴神经细胞自动机（NCA）的模式生成范式，它在退化的布尔搜索空间中导航，以满足计算任务，而非重复生成固定目标状态。实验表明，该方法可从零自组装出功能性电路，并迅速绕过永久性、此前未见的硬件故障。对于软错误，策略在损伤规模远超训练条件时仍实现近完美恢复（>99.99%准确率）。进一步观察到跨电路尺度的泛化能力：在比训练时大得多的图上，准确率反而提升。本工作将生物自组织原理与数字硬件实践相融合。
原文摘要 · Abstract (English)
Fault tolerance in classical computing has traditionally relied on static strategies like hardware redundancy and error-correcting codes. Biological systems, in contrast, exhibit adaptive plasticity, maintaining function through dynamic re-organisation around damage. Inspired by this principle, we introduce Self-Organising Digital Circuits, framing functional logic generation and maintenance as a meta-learning problem on graphs. Our architecture employs a topology-masked Transformer that configures the Lookup Tables (LUT) of a circuit's Boolean gates. Extending the pattern-generation paradigm of Neural Cellular Automata (NCA), it navigates the degenerate Boolean search space to satisfy a computational task, rather than regenerating a fixed target state. We demonstrate that it can self-assemble functional circuits from scratch and rapidly re-route logic around permanent, previously unseen hardware faults. For soft errors, the policy achieves near-perfect recovery (>99.99\% accuracy) from damage sizes far exceeding training conditions. We further observe generalisation across circuit scales: accuracy improves on graphs substantially wider than those seen during training. This work bridges the principles of biological self-organisation with the practical domain of digital hardware.
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