用智能体框架分析芯片设计中的海量工具文件，提升调试与优化效率。
EDATracer: An Agentic Framework for Large-Scale EDA Artifact Analysis
- 构建知识图谱+向量索引，跨文件类型检索设计证据。
- 在90个任务上平均准确率超同类工具6.4~7.2个百分点。
- 适合芯片设计工程师与自动化工具研发者参考。
现代芯片设计依赖电子设计自动化（EDA）工具生成大量异构数据，包括源代码、脚本、日志、网表和报告。分析这些数据对调试、优化和理解设计流程至关重要，但困难在于相关证据常分散于多种文件类型和设计阶段。尽管大模型智能体在辅助设计方面展现潜力，现有方法缺乏公开的大规模跨文件分析基准，且常难以基于工具生成的证据进行推理。我们提出EDATracer，一种基于证据的EDA工具分析智能体框架。该框架将设计数据组织为知识图谱与语义向量索引，使大模型能跨源文件、日志、网表和报告检索证据。我们整理了18.9 GB的2,787个可综合开源芯片设计数据集，并引入涵盖事实性、统计性和推理性任务的90题基准测试。在评估的多个智能体中，EDATracer在pass@1准确率上表现最佳，平均优于Cursor和Claude Code 6.4和7.2个百分点，同时使用2.0-3.2倍更少的令牌。
原文摘要 · Abstract (English)
Modern chip design relies on electronic design automation (EDA) tools that generate large, heterogeneous artifacts, including source files, scripts, logs, netlists, and reports. Analyzing these artifacts is critical for debugging, optimization, and design-flow understanding, but remains difficult because relevant evidence is often distributed across many artifact types and design stages. Although LLM agents show promise for EDA assistance, existing approaches lack public benchmarks for large-scale cross-artifact analysis and often struggle to ground reasoning in tool-generated evidence. We present EDATracer, an agentic framework for evidence-grounded EDA artifact analysis. EDATracer organizes design artifacts into a knowledge graph paired with a semantic vector index, enabling LLM agents to retrieve evidence across source files, logs, netlists, and reports. We curate an 18.9 GB dataset of 2,787 synthesizable open-source chip designs and introduce a 90-question benchmark spanning factual, statistical, and reasoning tasks. Across evaluated agents, EDATracer achieves the best pass@1 accuracy, outperforming Cursor and Claude Code by 6.4 and 7.2 percentage points on average, while using 2.0-3.2x fewer tokens.
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