芯片模块化与大模型融合带来新安全风险，本文系统分析并提出防御方案。
Hardware Design and Security in the Era of Chiplets and LLMs
- 从架构到物理层分析芯片模块系统的攻击面
- 提出2.5D分制造+主动中介层构建可信根防御机制
- 揭示大模型在EDA中潜在威胁，探索其反向赋能安全
半导体行业正经历双重变革：向异构2.5D芯片模块系统演进，以及将大型语言模型（LLMs）融入电子设计自动化（EDA）流程。尽管这些范式在良率、模块化、设计效率等方面带来显著优势，但也大幅扩展了硬件攻击面。本文对这一前沿领域进行统一分析，涵盖芯片模块系统（包括用于LLM加速的硬件堆栈）在架构、逻辑和物理层面的各类攻击，以及针对基于LLM的EDA流水线的多种漏洞利用。为保障芯片模块系统安全，本文综述了一种有效防御策略：利用2.5D分制造与主动中介层实现物理隔离的可信根（RoT）架构。针对基于LLM的EDA流程，首先识别其固有威胁，再回顾当前最先进的防护技术。最后，探讨了LLM系统如何反向推动现代系统（包括芯片模块）的安全能力提升。
原文摘要 · Abstract (English)
The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) flows. While these paradigms offer unprecedented benefits in yield, modularity, design productivity, etc., they radically expand the hardware attack surface. This paper provides a unified analysis of these frontiers, ranging from attacks on chiplet systems (including hardware stacks for LLM acceleration) across architectural, logical, and physical levels, to various exploits against LLM-driven EDA pipelines. To secure chiplet systems, we review a powerful defense approach that leverages 2.5D split manufacturing and active interposers for physically isolated Root of Trust (RoT) architectures. To secure LLM-driven EDA pipelines, we first identify native threats and then review state-of-the-art defense techniques. Finally, we discuss how LLM systems can advance hardware security efforts for modern systems, including chiplets.
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