用分层图模型分析电路时序，提升大规模设计的验证效率。
Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits
- 将电路分为寄存器间组合逻辑块和高层状态图两级表示
- 在大规模基准上使BMC求解时间减少18%且保证正确性
- 适合需要高效时序分析的集成电路验证工程师
电路表示学习（CRL）为电子设计自动化（EDA）核心任务提供了强大范式，但其实际应用受限于工业级网表的巨大规模以及未能显式建模寄存器级时序动态。为此，我们提出DeepSeq3，一种新颖的分层框架，将电路抽象为两级表示：由触发器（FFs）划分的细粒度组合子图，以及建模寄存器传输结构的高层超节点图（SNG）。采用双图神经网络架构，在两级上分别学习表示，捕捉局部布尔逻辑与全局状态转移。关键在于引入以状态为中心的预训练方案，预测触发器状态间的可达性，赋予模型对时序行为的深层理解。在大规模基准上的实证显示，DeepSeq3方法具备更优可扩展性与更丰富表示，使有界模型检查（BMC）求解时间降低18%，同时确保正确性。
原文摘要 · Abstract (English)
Circuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical adoption is hindered by the immense scale of industrial netlists and a failure to explicitly model register-level temporal dynamics. To overcome these barriers, we introduce DeepSeq3, a novel hierarchical framework that abstracts circuits into a two-level representation: fine-grained combinational subgraphs partitioned by flip-flops (FFs), and a high-level Super-Node Graph (SNG) that models the register-transfer structure. A dual Graph Neural Network (GNN) architecture learns representations at both levels, capturing local Boolean logic and global state transitions. Crucially, we introduce a state-centric pre-training scheme that predicts the reachability between FF states, endowing the model with a deep understanding of temporal behavior. Demonstrated on large-scale benchmarks, DeepSeq3's approach yields superior scalability and richer representations, reducing bounded model checking (BMC) solving time by 18% while guaranteeing correctness.
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