用图神经网络直接在网格上预测器件物理场,实现超快多尺寸晶体管设计探索。
Mesh-Native Physics-Informed Graph Surrogates for TCAD-in-the-Loop Design Space Exploration

- 在TCAD网格上构建物理感知图网络,直接预测电势和载流子能级
- 单器件推理时间不足1秒,吞吐量比真实仿真高多个数量级
- 支持跨结构迁移,适合大规模多目标设计优化场景
高保真漂移-扩散模拟仍是新兴鳍式场效应晶体管设计的核心工具,但其计算成本高昂,尤其在三维结构中,运行时间随网格复杂度急剧上升,严重限制了多目标设计空间探索。现有机器学习代理模型仅将固定设计参数映射为少数标量指标,丢失底层物理信息,且难以跨器件几何结构和类型迁移。本文提出一种物理感知图注意力网络(GAT)代理模型,直接在四面体TCAD网格上运行,对每个网格节点预测电势、电子和空穴准费米能级,即漂移-扩散系统的基本未知量。训练结合数据损失与有限体积电流连续性残差,将载流子输运物理嵌入目标函数。作为图结构操作,该代理具备规模泛化能力:在少量鳍结构上训练的模型可无修改应用于显著更大的阵列,推理仅受GPU内存限制。基于深度集成的节点级不确定性驱动主动学习循环,可在数秒内筛选大规模候选设计池,仅将最具信息量的设计送入完整仿真。在多鳍三栅鳍式晶体管上对比Sentaurus Device,该代理对三个漂移-扩散场的预测均达到亚伏每场均方根误差,且单设计吞吐量比全仿真高多个数量级。优势随器件尺寸增大而增强:对直接仿真极为耗时的大规模多鳍阵列,推理仍可在每器件不到一秒内完成,使无法通过直接TCAD扫描实现的跨尺度帕累托前沿探索成为可能。
原文摘要 · Abstract (English)
High-fidelity TCAD simulation of drift-diffusion transport remains the workhorse of emerging FinFET device design, but it is computationally expensive, especially for 3D structures where runtime escalates steeply with mesh complexity. This sharply limits multi-objective design space exploration. Existing machine-learning surrogates map a fixed set of design parameters to a few scalar device metrics, discarding the underlying physics and losing transferability across device geometries and families. A physics-informed graph attention network (GAT) surrogate is proposed. It operates directly on the tetrahedral TCAD mesh and predicts, at every mesh node, the electrostatic potential together with the electron and hole quasi-Fermi levels, the fundamental unknowns of the drift-diffusion system. Training combines a data loss with finite-volume current-continuity residuals, embedding carrier-transport physics into the objective. Operating on the mesh as a graph, the surrogate inherits size generalization: a model trained on few-fin meshes applies unchanged to substantially larger arrays, bounded at inference only by GPU memory. Per-node uncertainty from a deep ensemble drives an active-learning loop that screens large candidate pools in seconds and forwards only the most informative designs for full simulation. Benchmarked against Sentaurus Device on multi-fin tri-gate FinFETs, the surrogate reproduces the three drift-diffusion fields with sub-volt per-field RMSE and reaches a per-design throughput orders of magnitude higher than the full simulator. The advantage grows with device size: on large multi-fin arrays that are prohibitively slow to simulate directly, inference still completes in under a second per device, enabling Pareto-front exploration across device scales infeasible for direct TCAD sweeps.
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