用强化学习找量子电路，精准预测芯片制造中未知工艺与结构的性能。
A Unified Physics-Aware Quantum Machine Learning Framework across Power GaN HEMTs and Logic Nanowire FETs: Predicting Unseen Process Splits and Held-Out Geometry Combinations with Lower Error and Tighter Split-to-Split Variability
- 用图神经网络+强化学习自动搜索最优量子电路结构。
- 对两类晶体管的11个目标预测，误差降低59%~84%，波动更小。
- 无需物理规则约束，仍保持高精度和物理一致性，适合芯片设计优化。
我们提出一种统一的强化学习框架，用于在数据稀缺情况下建模功率GaN HEMT和逻辑纳米线FET器件。基于图神经网络（GNN）的策略通过近端策略优化（PPO）训练，利用留一组外交叉验证（LOGOCV）误差作为奖励，搜索紧凑参数化量子电路（PQC）架构。该框架在所有11个目标上的平均绝对误差（MAE）低于六种经典基线模型；对HEMTs，Ioff误差降低59%，阈值电压（VTH）波动减少81%；对NWFETs，VTH、SS、Ioff误差降低84%，Ioff波动减少82%。结果表明，尽管未引入显式物理约束、惩罚项或器件方程，由强化学习选择的类经典模拟量子电路仍可作为紧凑代理模型，实现低域外误差（OOD）和更好的物理一致性。
原文摘要 · Abstract (English)
We present a unified reinforcement-learning (RL) framework that discovers compact parametrized quantum circuits (PQCs) for data-scarce device modeling. A graph neural network (GNN) policy optimized by proximal policy optimization (PPO) searches circuit architectures using leave-one-group-out cross-validation (LOGOCV) error on held-out process or geometry groups as the reward. The framework achieves the lowest mean absolute error (MAE) on all 11 targets versus six classical baselines, with 59% lower error (Ioff) and 81% tighter fold variability (VTH) for HEMTs and 84% lower error (VTH, SS, Ioff) and 82% tighter fold variability (Ioff) for NWFETs. These results demonstrate the potential of RL-selected, classically simulated PQCs as compact surrogates with low OOD error and improved physical consistency, despite imposing no explicit physical constraints, penalty terms, or device-specific equations, on the two evaluated device datasets.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。